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Espressif Systems /ESP32-S3 /SENS /SAR_PERI_RESET_CONF

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Interpret as SAR_PERI_RESET_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SAR_COCPU_RESET)SAR_COCPU_RESET 0 (SAR_RTC_I2C_RESET)SAR_RTC_I2C_RESET 0 (SAR_TSENS_RESET)SAR_TSENS_RESET 0 (SAR_SARADC_RESET)SAR_SARADC_RESET

Description

the peri reset of rtc peri

Fields

SAR_COCPU_RESET

enable ulp-riscv reset
SAR_RTC_I2C_RESET

Reserved.
SAR_TSENS_RESET

enbale saradc reset
SAR_SARADC_RESET

enable io_mux reset

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data